The #Pineapple-One’s instruction memory board design, unfortunately in EAGLE. #electronics #hardware #RISC-V
on 02026-09-03overview of the #PULP #RISC-V #hardware family, with PULPino, PULPissimo, etc.
on 02026-09-03Western Digital’s SweRV #RISC-V cores, archived repository
on 02026-09-03The #PULP architecture family from #ETH Zurich augments #RISC-V with #hardware zero-overhead loops and post-increment addressing. #ISA
on 02026-09-02The new #RISC-V unprivileged #ISA #PDF is 696 pages and includes Zba and Zbb.
on 02026-06-03#roconnor wrote a combinator graph reduction machine in #RISC-V #asm #toread
on 02026-05-26#cpldcpu got 99.5% MNIST accuracy with variable quantization and depthwise separable convolution on a CH32V002, a newer, smaller #RISC-V #CH32V003 with multiplier #hardware. #microcontrollers #electronics #hardware #neural-networks #toread
on 02026-04-29#Bunnie helped design “the Baochip-1x, a mostly open source 22nm SoC”, with an improved version of the #RP2350’s PIO peripheral. Instead of a special-purpose instruction set like PIO, you have BIO, four of Claire Xenia Wolf’s PicoRV32 #RISC-V processors each with 4KiB of RAM, running at 700MHz, modified with a trick from his PhD thesis ADAM to map the non-RV32E registers to FIFOs; also they can DMA to and from the main CPU’s RAM. But it’s slower than PIO, can’t bitbang DVI. #Baochip #electronics #hardware #toread
on 02026-04-09#RISC-V #asm conditional moves and the 64-bit #ARM CSEL instruction #toread
on 02025-10-02discussion of #RISC-V #asm conditional moves and the 64-bit #ARM CSEL instruction
on 02025-10-02#RISC-V test suite that CNLohr said was really hard to use
on 02025-07-30#CNLohr #video explaining how he built a no-MMU Linux with #buildroot for his #RISC-V emulator. Gives debugging tips, like how to test your buildroot-built system image in QEMU, and how execution starts at the first byte of the image. Includes a Make #tutorial. Reveals that his name is Charles Lohr.
on 02025-07-30The #RVC #RISC-V emulator for #HLSL #shaders
on 02025-07-30"RVC" is a #RISC-V (rv32ima/su+Zifencei+Zicsr, Linux-capable) emulator on the GPU in an #HLSL pixel shader for #VRChat #shaders
on 02025-07-30“buildroot fork from damien -- RV32 no MMU Linux. Run “make qemu_riscv32_nommu_virt_minimal_defconfig” then “make”” This is what #CNLohr used to run Linux and #Duktape on his #RISC-V emulator.
on 02025-07-30#news on the #RISC-V Summit in China: high #performance implementations including “UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3”, which are mostly RVA23-compliant.
on 02025-07-27#Forth for #RISC-V: comparison operator implementations
on 02025-05-20"DC-ROMA" laptop with 8-core #RISC-V chip, I think using a 2GHz #SpacemiT K1 X60.
on 02024-09-27Banana Pi #SpacemiT 8-core #RISC-V SBC. 50 GIPS #performance, supposedly, 30% higher performance per core than ARM Cortex-A55. 256-bit RVV 1.0.
on 02024-09-27“Bianbu Linux is the BSP (Board Support Package) for the #Spacemit Stone series chips, including the SDK (Software Development Kit).” #RISC-V
on 02024-09-27A Banana Pi SBC with a #RISC-V #SpacemIT K1 X60 chip.
on 02024-09-27#performance on “the Shenzhen Milk-V Jupiter #RISC-V mini-ITX motherboard” based on the K1 processor. Lots and lots of photos. “an octa-core #SpacemIT X60 SoC with PowerVR B-Series BXE-2-32 GPU, 15.5 GB RAM (available to Linux).” The benchmarks are things like video decoding and OpenGL.
on 02024-09-27aiming at high #performance: “The #SpacemiT X60™ Intelligence Core is an advanced multi-core and multi-cluster #RISC-V RVA22 processor, equipped with RISC-V Vector 1.0 extensions and SpacemiT IME Intelligence Extensions, specifically optimized for general AI applications at the edge. (...) 2 TOPs@INT8 AI computing power compliant with RISC-V IME extensions. (...) 2.0GHz@22nm. (...) 3.66DMIPS/MHz. (...) 8-stage dual-issue in-order execution.”
on 02024-09-27The Milk-V Pioneer has a 64-core 2GHz #RISC-V SOPHON SG2042 with RV64GC and XTheadVector (based on RVV 0.7.1). This page has performance #benchmarks.
on 02024-09-16Zmmul is the #RISC-V instruction set extension for multiplication without division (what the M extension should have been)
on 02024-09-16#RISC-V laptop with a 1.5GHz quad-core #StarFive JH7110 (with four #SiFive U74s in it) with an integrated GPU
on 02024-09-14the #RISC-V #SiFive U74 core in the #StarFive JH7110 is about 2.5 #Dhrystone MIPS per MHz, while Roy Longbottom says the Cortex-A53 in the Raspberry Pi 3 is about 2.95 Dhrystone MIPS per MHz #performance
on 02024-09-14#LCSC #pricing for #CH32V003 #electronics #hardware is 12.45¢ in quantity 500. These are #RISC-V #microcontrollers
on 02024-08-27#PDF from 02019 by James Brakefield listing mostly open-source #microcontrollers #gateware on #OpenCores, including a bunch of #6502 designs, an RCA 1802 or two, some Motorola 6801 clones, a bunch of #8051 clones, several #8080 designs (including one by C.H. Ting!), several #68000 designs, several #68HC11 designs, several ARMs (which are not all proprietary), some #AVR designs, a lot of #Forth chips, a PDP-1, a bunch of MIPS designs, an MMIX, various #OpenRISC 1000 designs, a PDP-10, a bunch of PDP-8s, a lot of PIC16s, a lot of #RISC-V designs, Cray-1 and Cray-2 clones, several Z80s, the #Reduceron, etc. There’s a table specifying how many LUTs each one achieves, how many KIPS per LUT (!), what they’re written in, how big their address spaces are, year started, year of last revision, etc.
on 02024-08-25#RISC-V vector extension #video by #LaurieWired aimed at super beginners, explaining an #asm example line by line, then walking through it in GDB; apparently the Kendryte Canaan K230 chip supports RVV 1.0. But she doesn’t even mention T-Head, so I’m not sure I can trust her information. Like, her example assembly program doesn’t loop, and I think it needs to loop in case the vector registers on the hardware are less than 256 bits. Like, I think she needs something like blt t2, a3, loop_start to get the vector length agnosticism she’s talking about at the beginning but never explains.
#Bitluni wrote an assembler and interpreter for a new CHIP-8-like bytecode in one day on stream. #video of his 10¢ CH32V003 240-LED matrix board. He wants to switch to a CH32X035, which sounds like it might not be #RISC-V, but has USB-C support built in. Previously he had the buttons on a resistor ladder. He has a tiny little postage-stamp-sized hotplate to reflow his QFNs. If you short D+ to Vcc at powerup time it goes into programming mode and you can install new firmware. #electronics #hardware
on 02024-05-19“this #RISC-V cyberdeck is not for you.” Sponsored product review #video on the Sipeed Lichee Console 4A which can play YouTube in 480p and has gigabit Ethernet, despite being ten times slower than tiny Intel netbooks. 1280×720. Clitmouse. 600 grams. Touchscreen. Webcam. You can type on it faster than an iPad. Quad-core #T-Head C910 processor (TH1520), underclocked to 1.5GHz. 4.4 gigaflops. GPU is Imagination PowerVR, with performance similar to the Raspberry Pi 4.
on 02024-04-04it looks like maybe the #RISC-V #GD32V #GD32VF103 #hardware from #GigaDevice runs its code from SRAM, not Flash
on 02024-03-05a #RISC-V devboard from IAR with the #GigaDevice #GD32V #GD32VF103 #hardware on it (article from 02020)
on 02024-03-05Apparently you can run #RISC-V Linux on an #ice40 or at least a Lattice ECP5 now, on a versa_ecp5 board? And this package includes all the deps and has an easy-to-use script and getting-started guide?
Claire Wolf’s "PicoRV32" small #RISC-V implementation (with no MMU?)
on 02024-01-25Sipeed Lichee Console 4A #RISC-V mini-laptop review
on 02024-01-14#RISC-V self-hosting on #FPGA #hardware, enough to run Fedora Linux on
on 02023-10-08#USA #politics: Republican Senator Marco Rubio, Democratic Senator Mark Warner, Representative Mike Gallagher, (chairman of the House select committee on China) and Representative Michael McCaul, chairman of the House Foreign Affairs Committee line up in favor of export controls against #RISC-V
on 02023-10-08Looks like the #T-Head #RISC-V #hardware fails to implement #floating-point underflow correctly, at least the C910, C920, and probably C906, and in particular the LicheePi 4A.
on 02023-09-05Here’s how the #Linux kernel generates stack backtraces on #RISC-V by walking a chain of stack frames linked by frame pointers. With alloca() and variable-length arrays, the stack pointer alone isn’t enough to find your local variables.
on 02023-09-02the #RISC-V calling-convention #PDF: x2 (sp), x8 (fp/s0), x9 (s1), and x18–27 (s2–11) are call-preserved; x3 is the global pointer gp, which you need to preserve even for callees; and x4 is the thread pointer tp, which likewise. But x1 (ra/lr), x5–7 (t0–2), x10–17 (a0–7), and x28–31 (t3–6) are call-clobbered. a0–1 are return-value registers, making the same mistake as in the ARM calling convention. The stack pointer is always kept 16-byte (!!) aligned. Note that most RVC instructions can only access x8–x15 because their register fields are 3 bits; those are the call-preserved fp/s0 and s1 and the call-clobbered x10–15 (a0–5).
on 02023-09-02#booting with "EBBR", a subset of #UEFI, referenced by the #ARM Base Boot Requirements and the #RISC-V Platforrm Specification. #CC by-sa
on 02023-08-19#RISC-V #vectorization intrinsics search
on 02023-07-15apparently #RISC-V #vectorization on the T-Head core speed up most ffmpeg inner loops by a factor of 2–4
on 02023-07-13supposedly #RISC-V had shipped ten billion cores as of July 02022, which is apparently a number RVI CEO Calista Redmond announced
on 02023-07-13how to invoke Linux system calls on #RISC-V.
on 02023-07-08#RISC-V #performance simulation, covering #SeRV, #PicoRV32, Minerva, Hazard3, FemtoRV32, #VexRiscv, and the author's own Misato.
on 02023-07-08Graeme Smecher’s "Minimax" #RISC-V implementation is really an RV32C native core which emulates non-compressed RV32I instructions by trapping to millicode, using 116 FFs and 398 CLB LUTs, which is crudely maybe 2000 gates or 8000 transistors, not counting the memory. 16 RV32E registers, 512 bits, are maybe another 4096 transistors, bringing the total to maybe 12000: roughly three times the size of the Intersil 6100 or the 6502, and about a fourth the size of the Cortex-M0. This “compressed-first” or “RVC-first” approach is really interesting to me. #small-is-beautiful #electronics #hardware
on 02023-07-07apparently #tcc (#tinycc) supports #RISC-V now?
on 02023-07-03how to run the "NuttX" #RTOS on #RISC-V in #QEMU, with a disassembly of #boot code
on 02023-06-24#RISC-V #CFI control-flow integrity extension Zicfisslp for #security against ROP (return-oriented programming) etc.
on 02023-06-22why #RISC-V didn't build on #OpenRISC
on 02023-06-04apparently the #PicoRV32 implementation of #RISC-V runs at 12MHz or 24MHz on an ice40UP5k #iCE40 #FPGA but gets half a #Dhrystone MIPS per MHz
on 02023-05-25A compiler for the "B" programming language from which #C grew, written in modern times to be compatible with the original bytecode interpreter, with backends for #PDP-8 (unfinished), #PDP-11, amd64, #RISC-V (64), and #MIPS (32); by the retrocomputerist #aap from Berlin, who has squoze.net. #history
on 02023-02-16“[the WCH CH32V003 is] quite timely as we were forced by HQ last Friday to revise all product line designs to comply with 100% Chinese domestic semiconductors & passive components by latest Q4 end. All western sourced/accounts and parts are now forbidden, apart from those sourced by HQ’s registered jurisdiction.
Worth adding to the list, we’ve also signed accounts with GigaDevice and Expressif Shanghai in the MCU and connectivity range. (...) We’re in France BTW.” #hardware #politics #China #sanctions #RISC-V
on 02022-11-01but #Debian autobuilds for alpha, amd64, arc (!?), arm64, hppa, i386, ia64, m68k, mips, mips64, ppc, ppc64, rv64 (#RISC-V), s390x, sh4, and sparc64, plus some endianness variants
on 02022-09-16"SeRV", the smallest #RISC-V implementation, fits into 200 4-LUTs
on 02022-06-02#MIPS says their #RISC-V IP cores, the eVocore P8700 and I8500, are/will be the fastest
on 02022-05-21Claire Wolf got her PicoRV32 #RISC-V soft-core, which can run on an iCE40, to synthesize SSI TTL #hardware with #yosys. The result was a design with 4'846 chips.
on 02021-09-12more on #Xuantie; "T-Head" is the open-source #hardware group at #Alibaba. #RISC-V
on 02021-05-29#Alibaba #Xuantie by Pingtouge Semiconductor (“brother pingtou” or “honey badger”) #hardware #RISC-V
on 02021-05-29Why #RISC-V doesn’t yet support #KVM; looks like #Linux will change some RISC-V policies
on 02021-05-29"Pineapple One" #RISC-V #hardware. Mentions that the reason for using 100mm×100mm PCBs is that they’re cheaper at #JLCPCB.
on 02021-05-29Filip Szkandera built a 500kHz 32-bit #RISC-V CPU called the #Pineapple-One; first he simulated it in #Logisim-Evolution, then laid it out as 230 or so chips on 8 100mm×100mm PCBs, mostly 74HCT chips. #hardware
on 02021-05-29more discussion of #RISC-V’s imperfections
on 02021-02-09another person criticizing #RISC-V, David Chisnall, previously head of a RISC-V WG
on 02021-02-09#video of an ARM engineer who does like #RISC-V in 02019, says it’s state of the art
on 02021-02-09why an ex-ARM engineer doesn’t like #RISC-V
on 02021-02-09the #Selfie subset of #RISC-V, called "RISC-U", has 14 instructions (including limited multiply and divide) but omits AUIPC and URET/SRET/MRET
on 02021-02-09"Selfie" #bootstrapping #RISC-V
on 02021-02-09#ebook about #Selfie, the #bootstrapping system that emulates a subset of #RISC-V and compiles itself from a subset of #C and has a #SAT #solver for bounded model checking
on 02021-02-09discussion of why the #RISC-V #hardware architecture doesn’t have condition code flags, veering off into crypto
on 02021-02-09A new #ESP32 #microcontroller "ESP32-C3" with #RISC-V RV32IMC has better single-core #performance but less RAM
on 02021-02-09how booting works on #RISC-V
on 02021-02-09#RISC-V #hardware design aimed at super low power, the basis for the #GD32 GD32V line, by way of Nucleisys’s Bumblebee (which is cited in the GD32VF103 user manual from GigaDevice: “The devices of GD32VF103 series devices are 32-bit general-purpose microcontrollers based on the Nuclei Bumblebee processor.”)
on 02020-01-25apparently you can get Picorv32 #RISC-V to run on a #iCE40 #FPGA #hardware
on 02021-01-24#RISC-V #hardware manuals, #CC by
on 02021-01-24notes on running #RISC-V on #FPGA #hardware (the ULX3S; sidenote, looks like Gitter is using the Matrix) and writing an OS for it, and how he got his workflow from editing code to rebooting the kernel on hardware down to a few seconds
on 02021-01-24a comparison #paper on ten (!!) #RISC-V implementations for #FPGA #hardware, mysteriously excluding VexRiscv, which has configurations much smaller and faster than anything they tested
on 02021-01-24"VexRiscv" itself, the #RISC-V implementation that fits into 504 #FPGA #hardware LUTs and 505 flip-flops on an Artix-7
on 02021-01-2402019 article on #hardware #security against #Karger-Thompson attacks with #bootstrappable #RISC-V, from CERT, which has apparently been captured by the SEI. Explains command-line by command-line how to build a system
on 02021-01-24#VexRiscv can run #RISC-V on Lattice ECP5 #FPGA #hardware (and, I think, even on an iCE40), and on the ECP5 can even run Linux on LiteX
on 02021-01-24SiFive’s US$665 HiFive Unmatched board uses a 5-core 1.4 GHz #RISC-V #hardware "FU740" or “Freedom U740” comparable to the #Raspberry-Pi 4’s quad-Cortex-A72. #performance of 2.5 DMIPS/MHz and 4.9 CoreMark/MHz (from which we can deduce that a CoreMark is about 2 #Dhrystone MIPS), dunno if this is per-core or per-chip.
on 02021-01-24#Alibaba's 2.5-GHz 16-core #RISC-V monster "CoreXuanTie910" or XT910 RV64GCV #hardware built in a 12nm process, in 02019. #xuantie
on 02021-01-24advice on #emulation of #RISC-V for learning: qemu-system-riscv32 -S -s -kernel /path/to/myprog.elf -nographic
not-for-profit #RISC-V company focused on "OpenTitan", the “first transparent silicon root of trust” #Karger-Thompson #hardware #security
on 02021-01-24a #RISC-V implementation in 7400-series #hardware — incredible and maybe a bit perverse. Each of the registers in the 16-register register file, for example, is on a separate 8-chip circuit board.
on 02017-03-22onchipUIS wants to make #free-software #hardware: “have designed and taped out a #RISC-V implementation with Cortex M0-like characteristics.”
on 02016-10-10“The Freedom #FPGA Development Kits are the ideal way to start software development for the #RISC-V ecosystem” #hardware
on 02016-07-11“Arty” is a US$100 #hardware development board based on Xilinx’s Artix-7 #FPGA, designed for use with the MicroBlaze processor soft core. Maybe you can run #RISC-V on it?.
on 02016-07-11the #RISC-V #free-software core is written in the #Chisel #HDL.
on 02016-01-14