"GateMate", a new (well, since 02020) #FPGA that supports #Yosys etc., made in 28nm at GlobalFoundries Dresden. They’re using 2-LUTs but have a 2×2-bit multiplier in each 8-input logic block. #hardware #electronics
on 02026-06-22apparently #VexRiscv and also #PicoRV32 supports the #iCE40 UP5K #hardware multipliers now (there are 8) because #Yosys can infer them as of last year
on 02023-09-02to use the single-ported RAM on a #Lattice #iCE40 #FPGA you have to tell #Yosys explicitly to instantiate an SB_SPRAM256KA
notes from a #tutorial workshop on how to use #Yosys with the #Skywater PDK, etc., as part of "OpenLANE" #hardware #electronics
on 02023-07-08#PDF of the original #yosys #paper from 02013
on 02023-07-08Claire Wolf got her PicoRV32 #RISC-V soft-core, which can run on an iCE40, to synthesize SSI TTL #hardware with #yosys. The result was a design with 4'846 chips.
on 02021-09-12now #yosys can synthesize a #KiCad netlist for SSI logic #hardware with #SKiDL, and #GHDL enables it to take #VHDL input instead of just #Verilog.
on 02021-05-29"APIO" is a sort of distribution similar to gEDA: “Open source ecosystem for open #FPGA boards. Apio (pronounced [ˈa.pjo]) is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your #verilog designs.” #hardware #yosys
on 02021-01-13