Human Folly about “VexRiscv”

(youtube.com):
#video of Linux booting on #Flea86’s #VexRiscV #FPGA SBC (now private)
on 02026-05-20
Fwlypfc (imgur.com):
#Flea86 has a new #FPGA PCB that can boot Linux on #VexRiscV
on 02026-05-20
(github.com):
apparently #VexRiscv and also #PicoRV32 supports the #iCE40 UP5K #hardware multipliers now (there are 8) because #Yosys can infer them as of last year
on 02023-09-02
20220118 ASIC roundup of open source riscv CPU cores (bitlog.it):
#RISC-V #performance simulation, covering #SeRV, #PicoRV32, Minerva, Hazard3, FemtoRV32, #VexRiscv, and the author's own Misato.
on 02023-07-08
Blog (bunniestudios.com):
#Bunnie’s #Precursor is currently using #VexRiscv on Spartan #FPGA #hardware to defeat #Karger-Thompson #hardware attacks (and other hardware #security problems) but most of the FPGA is devoted to #crypto, mostly cores from #OpenTitan
on 02021-01-24
VexRiscv (github.com):
"VexRiscv" itself, the #RISC-V implementation that fits into 504 #FPGA #hardware LUTs and 505 flip-flops on an Artix-7
on 02021-01-24
Lattice FPGA SBCs can run Linux on RISC V softcore (linuxgizmos.com):
#VexRiscv can run #RISC-V on Lattice ECP5 #FPGA #hardware (and, I think, even on an iCE40), and on the ECP5 can even run Linux on LiteX
on 02021-01-24