"RIO Core" is a real time I/O thingy for #LinuxCNC motion control which runs the hard-real-time stuff on an #FPGA, using #gateware custom-generated for parameters input through a GUI
on 02026-03-19#Lisp machine #gateware for the MIT CADR in modern #Verilog. “Boots and runs.” By #lisper (Brad Parker)
on 02024-08-25#PDF from 02019 by James Brakefield listing mostly open-source #microcontrollers #gateware on #OpenCores, including a bunch of #6502 designs, an RCA 1802 or two, some Motorola 6801 clones, a bunch of #8051 clones, several #8080 designs (including one by C.H. Ting!), several #68000 designs, several #68HC11 designs, several ARMs (which are not all proprietary), some #AVR designs, a lot of #Forth chips, a PDP-1, a bunch of MIPS designs, an MMIX, various #OpenRISC 1000 designs, a PDP-10, a bunch of PDP-8s, a lot of PIC16s, a lot of #RISC-V designs, Cray-1 and Cray-2 clones, several Z80s, the #Reduceron, etc. There’s a table specifying how many LUTs each one achieves, how many KIPS per LUT (!), what they’re written in, how big their address spaces are, year started, year of last revision, etc.
on 02024-08-25#OpenCores has a custom search engine page (“CSE”) on Google for searching for #hardware #gateware designs
on 02024-08-25Goran Devic’s cycle-accurate LGPL-licensed #Z80 core simulator the "A-Z80" #retrocomputing #gateware
on 02024-06-16LGPL #ARM v2a for a Spartan-6 in #Verilog. #gateware
on 02023-07-01Andres Navarro’s GPL-licensed #VT52 #terminal #gateware in Verilog, 2000 LUTs including USB, PS/2, and VGA, with no processor; buildable with Icestorm #retrocomputing
on 02022-09-16