Human Folly about “SeRV”

index

• 20220118 ASIC roundup of open source riscv CPU cores (bitlog.it):

  #RISC-V #performance simulation, covering #SeRV, #PicoRV32, Minerva, Hazard3, FemtoRV32, #VexRiscv, and the author's own Misato.

  on 02023-07-08
• SeRV (github.com):

  "SeRV", the smallest #RISC-V implementation, fits into 200 4-LUTs

  on 02022-06-02