#GateMate #FPGA #electronics #hardware #PDF #datasheet
on 02026-06-22Hannah Ravensloft’s #PDF schematics of the #GateMate #FPGA #hardware design. #electronics
on 02026-06-22"GateMate", a new (well, since 02020) #FPGA that supports #Yosys etc., made in 28nm at GlobalFoundries Dresden. They’re using 2-LUTs but have a 2×2-bit multiplier in each 8-input logic block. #hardware #electronics
on 02026-06-22#FPGA #keyboards with #Nyancat and 8000Hz sampling
on 02026-05-28#video of Linux booting on #Flea86’s #VexRiscV #FPGA SBC (now private)
on 02026-05-20#Flea86 has a new #FPGA PCB that can boot Linux on #VexRiscV
on 02026-05-20“An attempt to recreate the #RP2040 PIO in an #FPGA” gateware similar to the #RP2350 #electronics #hardware. Bunnie recommends using it to debug your PIO code with Verilator.
on 02026-04-09"RIO Core" is a real time I/O thingy for #LinuxCNC motion control which runs the hard-real-time stuff on an #FPGA, using #gateware custom-generated for parameters input through a GUI
on 02026-03-19Apparently WDC had a 65C832 32-bit 6502 in the works, but never got it built, so Mike Kohn built one in an #FPGA from the datasheet. #electronics #Verilog
on 02025-08-25Tips for creating a #FPGA ULPI #USB interface. #electronics #toread
on 02025-08-03FleaFPGA Experimenters Board. UPDATE 17/12/2016: This product has now been retired. By #Flea86? #FPGA #hardware
on 02025-06-12#RISC-V self-hosting on #FPGA #hardware, enough to run Fedora Linux on
on 02023-10-08the only successful #PDP-10 on an #FPGA is the "PDP-10/X". It boots ITS.
on 02023-09-19#KV10 is a #PDP-10 on an #FPGA, work in progress
on 02023-09-19"KV10" is another attempt to simulate a #PDP-10 on an #FPGA
on 02023-09-19#CHERI #Morello #hardware initial results show 15% #performance overhead on SPECint2006 for #capability-systems #security, but simulations on #FPGA suggest ways to reduce this to 1.8–3.0%.
on 02023-09-19the "Jurassic-20" is yet another attempt to reproduce #PDP-10 #hardware on an #FPGA: “totally a playground work in progress.”
on 02023-09-19to use the single-ported RAM on a #Lattice #iCE40 #FPGA you have to tell #Yosys explicitly to instantiate an SB_SPRAM256KA
This is Charles Eric LaForest’s page about CPU design using #FPGA #hardware, mostly focused on #stack-machines and #Forth; he did his BIS at Waterloo, and his thesis contains the best explanation I’ve seen of why stack machines went out of favor.
on 02023-08-09OpenFPGA is an #FPGA #softcore with two 4-LUTs per CLB which has been fabricated (?) in the #Skywater #efabless program. #hardware
on 02023-07-09apparently the #PicoRV32 implementation of #RISC-V runs at 12MHz or 24MHz on an ice40UP5k #iCE40 #FPGA but gets half a #Dhrystone MIPS per MHz
on 02023-05-25apparently you can get Picorv32 #RISC-V to run on a #iCE40 #FPGA #hardware
on 02021-01-24#Bunnie’s #Precursor is currently using #VexRiscv on Spartan #FPGA #hardware to defeat #Karger-Thompson #hardware attacks (and other hardware #security problems) but most of the FPGA is devoted to #crypto, mostly cores from #OpenTitan
on 02021-01-24notes on running #RISC-V on #FPGA #hardware (the ULX3S; sidenote, looks like Gitter is using the Matrix) and writing an OS for it, and how he got his workflow from editing code to rebooting the kernel on hardware down to a few seconds
on 02021-01-24a comparison #paper on ten (!!) #RISC-V implementations for #FPGA #hardware, mysteriously excluding VexRiscv, which has configurations much smaller and faster than anything they tested
on 02021-01-24"VexRiscv" itself, the #RISC-V implementation that fits into 504 #FPGA #hardware LUTs and 505 flip-flops on an Artix-7
on 02021-01-24#VexRiscv can run #RISC-V on Lattice ECP5 #FPGA #hardware (and, I think, even on an iCE40), and on the ECP5 can even run Linux on LiteX
on 02021-01-24#Bunnie’s proposal to make “trustable” #hardware with an #FPGA #security #bootstrappable #Karger-Thompson
on 02021-01-20The tinyVision.ai UPduino v3.0 Board Features: Lattice UltraPlus ICE40UP5K #FPGA with 5.3K LUTs, 1Mb SPRAM, 120Kb DPRAM, 8 Multipliers; 4MB SPI Flash; #APIO support; etc.
on 02021-01-13"APIO" is a sort of distribution similar to gEDA: “Open source ecosystem for open #FPGA boards. Apio (pronounced [ˈa.pjo]) is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your #verilog designs.” #hardware #yosys
on 02021-01-13#PDF of Chuck Thacker's "Tiny Computer for Teaching" #hardware design for a 32-bit Harvard RISC computer with 4KiB each of instruction and data RAM, based on the Dirty Genitals Nova, occupying 83 lines of Verilog source (if I counted right) and 200 LUTs and four BRAMs on a Xilinx Virtex-5 #FPGA, getting 60 MIPS. #smallisbeautiful
on 02020-06-23The Project #Oberon book #PDF has a chapter about the #Wirth-RISC #hardware, largely the same as the people.inf.ethz.ch PDFs, but covering the Verilog in detail, and for example describing the floating-point format and logic, the PS/2 mouse protocol and its Verilog implementation on #FPGA, and quadrature decoding. #smallisbeautiful
on 02020-06-23The "OberonStation" #Oberon #FPGA #Wirth-RISC workstation site has gone offline but survives in the Archive for now.
on 02020-06-23#Yossi Kreinin’s #FPGA article
on 02018-09-24The #J1(a) #Forth processor on the Nandland #hardware, which has the ICE40HX1K #FPGA among those supported by #IceStorm.
on 02017-10-01AHA is Stanford’s Agile #Hardware Center, which aims to produce a fully open-source #FPGA toolchain and their own reconfigurable SoC, among other things
on 02016-10-14“The Freedom #FPGA Development Kits are the ideal way to start software development for the #RISC-V ecosystem” #hardware
on 02016-07-11“Arty” is a US$100 #hardware development board based on Xilinx’s Artix-7 #FPGA, designed for use with the MicroBlaze processor soft core. Maybe you can run #RISC-V on it?.
on 02016-07-11phased array passive sonar for #audio imaging, like what HASAS does for anti-submarine warfare; using MEMS microphones, it becomes affordable to feed a lot of microphones to a #FPGA #hardware at once for #DSP #beamforming. Like holy shit 65536 microphones. By Artem Litvinovich.
on 02016-06-29This ICE40LP1K-QN84 is I think the most-stocked-by-Digi-Key #FPGA supported by Project #IceStorm. It costs US$4.29, has 64 kibibits of RAM, and has 160 CLBs (LABs?) totaling 1280 LUTs
on 02015-11-09Digi-Key’s #2 most-stocked #FPGA #hardware is this US$14 Lattice thing, which is super interesting because Project IceStorm is for Lattice FPGAs. However, I think this is not one of the FPGAs #IceStorm supports, which are the iCE40 family; this is part of the "ECP2" family, which are “optimized for data and control path bridge and interfacing”.
on 02015-11-09A free-software #Forth operating system running on the J1a open-source CPU running on a Lattice #FPGA thanks to Project #IceStorm’s reverse engineering and the resulting free-software #synthesis and programming toolchain, running on the Lattice iCEstick evaluation board with 8K of RAM. #J1 #hardware
on 02015-08-28