Claire Wolf got her PicoRV32 #RISC-V soft-core, which can run on an iCE40, to synthesize SSI TTL #hardware with #yosys. The result was a design with 4'846 chips.
The CoolRunner-II #CPLD now has open-source place-and-route support in openfpga: xc2par by Robert Ou, which produces a .jed file (JEDEC I guess) which azonenberg’s jtaghal, among other things, can stuff down the CPLD. #hardware
one of the biggest CoolRunner-II #CPLD chips is the XC2C512, which has 512 macrocells in 32 function blocks and costs US$85. #hardware
the only potentially great people from Vilnius are Marija Gimbutas, Ludwik Zamenhof, Andrew Schally, and Czesław Miłosz
8-bit code page (charset) for #Arabic
Champion #code-golf #esolang Osabie, has some 400 built-in stack operations, including perfect shuffle, matrix diagonal, Lucas numbers, lcm, #shoco decompression and so on. I’m not sure what character set these are supposed to be in but it contains both Å and ζ. #compression
"shoco" short string #compression #algorithm never expands 7-bit ASCII and usually compresses it some (using the 8th bit), using an English bigram model.