Human Folly about “PicoRV32”

index

• PicoRV32 (github.com):

  Claire Wolf’s "PicoRV32" small #RISC-V implementation (with no MMU?)

  on 02024-01-25
• (github.com):

  apparently #VexRiscv and also #PicoRV32 supports the #iCE40 UP5K #hardware multipliers now (there are 8) because #Yosys can infer them as of last year

  on 02023-09-02
• 20220118 ASIC roundup of open source riscv CPU cores (bitlog.it):

  #RISC-V #performance simulation, covering #SeRV, #PicoRV32, Minerva, Hazard3, FemtoRV32, #VexRiscv, and the author's own Misato.

  on 02023-07-08
• Mecrisp quintus Forth with PicoRV32 on UPduino and 8 queens benchmark (eevblog.com):

  apparently the #PicoRV32 implementation of #RISC-V runs at 12MHz or 24MHz on an ice40UP5k #iCE40 #FPGA but gets half a #Dhrystone MIPS per MHz

  on 02023-05-25