PDOS/386 is a public-domain operating system that can run on #ARM as an Android app
on 02026-09-02#M5stack #Cardputer Zero #hardware is going on sale for an “early bird” price of US$59. Raspberry Pi Compute Module 0 (BCM2837, quad-core 1GHz #ARM Cortex-A53, 512MB LPDDR2 RAM, 46-key shitty keyboard, 1.9-inch ST7789v3 LCD screen, 1500mAh LiPo, Wi-Fi, Bluetooth #BLE) in credit-card 85×54mm form factor, but much thicker than a credit card
on 02026-05-22using #CH32V003 #microcontrollers for debugging connections to #ARM #electronics #hardware (alternative to ST-Link or J-Link) obtained by #hoarding disposable vapes. The protocol is CoreSight DAP (Debug Access Probe) over SWD, also implemented by CMSIS-DAP, DAPLink, or free-dap.
on 02025-11-11#RISC-V #asm conditional moves and the 64-bit #ARM CSEL instruction #toread
on 02025-10-02discussion of #RISC-V #asm conditional moves and the 64-bit #ARM CSEL instruction
on 02025-10-02Complete #ARM #SIMD #asm intrinsics list, including the strided things. Reference #documentation.
on 02025-09-28#ARM #asm #SIMD intrinsics for (vertical) addition. vaddq_u16 (vadd.i16) and the like.
This is the #ARM #documentation for the MOV32 pseudo-instruction consisting of MOV (now we call it movw) and #MOVT.
#ARM #documentation on loading constants in #asm, using constant pools, MOV, MVN, etc. “MOV can load any 8-bit constant value, giving a range of 0x0-0xFF (0-255). It can also rotate these values by any even number.” Adjacent sections of the manual explains LDR with constant pools and the MOV32 pseudo-instruction.
Similarly movs is allowed and mov is not in Thumb-1 #ARM #asm. As old_timer says, “The short answer is that you cannot because the instruction does not exist. If you are using unified syntax documentation that glosses over which instruction sets are supported, then you have, as many others, fallen into the trap of the major failing of the unified syntax.”
GNU assembler for #ARM #asm with .syntax unified insists that you write adds rather than add to compile to Thumb-1 code. And with Thumb-2 it will generate a wide add instruction if you don’t say adds. Notlikethat explains: “The only Thumb encodings for (non-flag-setting) mov with an immediate operand are 32-bit ones, however Cortex-M0 doesn’t support those, so the assembler ends up choking on its own constraints.” Similarly for mov vs. movs.
#ARM Cortex-M3 added a CLZ #bitmanip instruction, but this is an #asm version of it for more primitive ARMs.
on 02025-09-09#ARM #asm has movt and movw instructions in later Thumb2 versions; these permit you to load a 32-bit constant in two instructions, each supplying 16 bits. movw clears the high bits and movt loads them. This question pertains to #Clang needing -mthumb to assemble Thumb asm. #movt
The CLZ #asm #bitmanip instruction is __builtin_clz on GCC, but this page claims to have a 13-instruction-time version with better #performance than all the “Hacker’s Delight” entries, with “[bisection] to find out which 8-bit chunk of the 32-bit number contains the first 1-bit, which is followed by a lookup table clz_lkup[] to find the first 1-bit within the byte.” Handy for Cortex-M0 #ARM chips without the instruction.
#ARM CPUs (bigger than Cortex-M0 or Cortex-M0+) have a CLZ #bitmanip instruction to count the number of leading zeroes, and CMSIS-CORE has a __CLZ intrinsic function for when you aren’t in #asm. Also signed saturate, unsigned saturate, rotate right with extend, wait for event, etc.
The #ARM Cortex-M3 (used in many processors of the #STM32 line) has #performance of 1.25 #Dhrystone MIPS/MHz
on 02025-07-20200 billion #ARM chips, mostly #microcontrollers, had been shipped as of 02021; 1 billion as of 02022, and 1 billion a year in 02011. At the time of the article (02021-10-18) they were shipping 900 per second, which is about a billion every two weeks.
on 02025-03-28200 billion #ARM chips produced as of 02021, half of them Cortex-M, at which point they were 900 ARMs per second.
on 02025-03-26#LCSC #pricing for 14-pin #PY32 #ARM #microcontrollers #hardware, 9.01¢ in quantity 500. Not the cheapest, but it’s an ARM. #electronics
on 02025-03-16“This documentation details my experiences with building and installing mainline versions of OP-TEE, U-Boot and Linux for systems based on #Rockchip's RK3229. The primary focus of my efforts has been, and remains, on the Mecer Xtreme Mini S6,” #ARM
on 02024-08-31PSCI, the Power State Coordination Interface, is a standardized interface for #power-management on #ARM so Linux maintainers can suffer less
on 02024-08-31#ARM’s #ARM64EC (or Microsoft’s?) is a new #ABI for #ARM64 designed to facilitate calling back and forth between native code and emulated code, so in particular emulated binaries can dynamically link to native-code system libraries (DLLs); each entry point into an aarch64 library has an amd64 “fast forward sequence” which the emulated code calls. The OS kernel, however, maintains a bitmap to keep track of which pages contain native code and which contain emulated code.
on 02024-03-24#lcamtuf’s #introduction to #Atmel #ARM ATSAMS70J21 #hardware bringup from a year ago. “On an 8-bit MCU, adjusting the clock is trivial; on the SAM S70, you can try some online examples, realize that they’re all wrong, and then spend several hours nose down in the 2,000 page datasheet. (...) The first revelation is that 300 MHz is the maximum clock for the processor core (HCLK), not the entire device. There is an internal bus used by the flash memory controller and other built-in peripherals, and that bus can’t run faster than 150 MHz; this fact is helpfully mentioned on page 1852 of the spec.” #microcontroller
on 02024-03-06Initial #buck50 #Sigrok #logic-analyzer #STM32 firmware announcement from 02020. Including discussion of #performance and how it differs from the #ARM reference manual cycle counts.
on 02024-01-28#ARM offers gratis M1 and M3 cores “following free registration on the official website”, but only for designing an “integrated product”, not for reverse engineering, patent investigation, patent avoidance, patent writing, or benchmarking. Whew!
on 02024-01-12the 12940-page (!!) #PDF #documentation for #ARM A-profile (DDI0487)
on 02023-10-06#ARM Cortex-A72 #hardware “is a superscalar processor which predicts branch direction and executes instructions speculatively along predicted program paths.” for #performance.
on 02023-09-19to flush the instruction cache for #RTCG JIT #compilers on #ARM #Linux you need to make sure the memory is mapped with PROT_EXEC before you invoke sys_cacheflush or __clear_cache(). #hardware
#RTCG #hardware cache flush functions on #ARM: __clear_cache, cacheflush, or FlushInstructionCache.
#RTCG #hardware cache flush instructions on #ARM 64 #hardware for JIT #compilers
on 02023-09-19Fahlman asking if #SBCL #Lisp supports #ARM
on 02023-09-06#booting with "EBBR", a subset of #UEFI, referenced by the #ARM Base Boot Requirements and the #RISC-V Platforrm Specification. #CC by-sa
on 02023-08-19#ARM #asm addressing modes #PDF of lecture slides
on 02023-07-19#ARM #STM32 (specifically STM32L4xx/6xx, in this case STM32L486ZG) has a bug where it can't read a burst of 9 or more words from off-chip memory.
on 02023-07-19#GCC options for #ARM ABIs (-mabi=) are just apcs-gnu, atpcs, aapcs, aapcs-linux, and iwmmxt. But there's an option to reserve a register for PIC: -msingle-pic-base -mpic-register=r10.
on 02023-07-19#Android #AOSP #ARM #asm for #Linux system calls
on 02023-07-19#Linux #ARM system call interface (for #EABI), with a table of system calls and arguments. #asm
on 02023-07-19In #Linux on #ARM in #EABI, the system call arguments are in registers r0-r6, and the return value is in registers r0 and r1. #asm
on 02023-07-19Since #Linux 2.6, #ARM system calls under the #EABI use the swi 0 or svc 0 instruction with the system call number in R7 and arguments in r0-r5, with 64-bit arguments starting in an even register. #asm
Oh, no, the #ARM #EABI is from 02003 and RealView 2.0 and later #GCC 4.1.0 and Linux 2.6.16.
on 02023-07-19The #ARM #EABI was apparently introduced in 02007 or thereabouts.
on 02023-07-19The so-called #ARM #EABI is the standard ABI for #Linux, supplanting the so-called OABI. Explains how system calls work in #asm. Also explains the checkered history of interworking. Debian architecture “armel” is EABI, “arm” is OABI, dropped in Squeeze.
on 02023-07-19Raymond Chen's #ARM #asm #tutorial, section on bitwise ops.
on 02023-07-13Raymond Chen’s #ARM #asm #tutorial, section on cmn, which apparently doesn’t set the carry flag in the same cases that cmp with the negative would, specifically in the cases of comparing against zero and the most negative integer. More details on flag bits.
on 02023-07-13Raymond Chen’s #ARM #asm #tutorial. Section on arithmetic. Explains that in mvn the n is logical negation, while in cmn it’s arithmetic negation. And how to negate by reverse subtracting from literal zero.
on 02023-07-13Raymond Chen’s #ARM #asm #tutorial. Section on loading constants in one instruction, with mov, mvn, #movt, shifts, rotates, etc. This is the thing to read to understand how to generate constants on ARM, especially Thumb. “You can take your 8-bit unsigned immediate and shift it left by up to 24 positions, thereby allowing you to create any 32-bit constant where the span from the lowest to highest set bit is at most 8 positions. There are also a few special transformations (...) handy for setting up a register to fill memory with a repeating pattern. (...) In addition to all of the special constants that can be generated with MOV, you can use the MVN instruction to generate the bitwise NOT of them all.”
Raymond Chen’s #ARM #asm #tutorial covering the available addressing modes, including quirks like the absence of shifts other than left shift or more than three for byte or halfward access. Also how the Microsoft assembler says |foo| to mean “the address of foo” and how literal pools work.
The #Microsoft-Windows #ARM #asm ABI. It really does require that r11 always be a frame pointer! But then it softens that to a recommendation. It doesn’t seem to explain the IT/ITE/ITTE limitation mentioned in Raymond Chen’s blog post; possibly it’s gone?
on 02023-07-13Raymond Chen’s #ARM #asm #tutorial introduces #Thumb. The #Microsoft-Windows ABI only lets you conditionalize a single instruction with IT! You can’t use ITE, ITTE, ITEE, etc., at all there, because it doesn’t know how to recover from hardware interrupts.
on 02023-07-13First in Raymond Chen’s #tutorial about #ARM #asm; apparently #Microsoft-Windows 10 still supports 32-bit ARM, but only in #Thumb mode. This is the intro where he explains the register set, stack alignment constraints, flags, etc.
on 02023-07-13Raymond Chen’s #tutorial about #ARM #asm, section on common patterns in compiler-generated code: function pointer invocation, vtable invocation, control-flow guard.
on 02023-07-13The end of Raymond Chen’s #tutorial about #ARM #asm. Apparently Microsoft Windows does use the old convention where r11 points to a linked list of stack frames. The example code he walks through here uses push, add, mov, ldr, mvn, tst, beq, movs, str, b, ldr, subs, asrs, bl, and pop. The Microsoft assembler uses slightly different syntax.
on 02023-07-13Raymond Chen’s #tutorial about #ARM #asm, section on the APSR flags register, reading with mrs Rd, apsr and writing with msr apsr, Rn. Mentions a failure of virtualizability of the original ARM: privileged status bits read as 0 in user mode and ignore writes.
Raymond Chen's #tutorial about extending #ARM #asm branching instructions’ reach with “trampolines” or “veneers”, in particular bl, which is used for intra-module calls (when you know you’re not switching modes) but can only reach 16MiB away.
on 02023-07-13Raymond Chen's #tutorial about #ARM #asm branching instructions such as tbb.
on 02023-07-13#ARM #asm #Cortex-M4 technical reference manual, including instruction timings. #PDF
on 02023-07-12#tutorial on #binutils with #ARM focus, covering ELF, DWARF, etc.
on 02023-07-11shared libraries with multiple processes in a single address space requires a base pointer in a register or something; this is the #ARM standard for how this so-called "FDPIC" works
on 02023-07-11interview with #ARM designer Sophie Wilson about ARM’s #history. At 6'41" she says Nokia was "scared" about the (fairly poor) code density of ARM, which is where #Thumb came from: the desire to build mobile phones around it.
on 02023-07-09#ARM #Thumb instruction set encoding. Ugh. A full assembler in Lisp for Thumb. #asm
on 02023-07-08More on #ARM #Cortex-M0 and familly.
on 02023-07-06#ARM #Cortex-M0 is supposed to be 12000 logic gates; dr.indira says she thinks it’s 72000-100000 transistors. Joseph Yiu of ARM corrects dr.indira’s estimate, saying, “Without going into details, some of the low cost Cortex-M0 microcontrollers on the market has less than 50K gates and that included bus system, peripehrals [sic], and possibly DMA support, etc (exclude memory area and analog components). The 12K gate number is based on minimum configuration at 180ULL process.”
on 02023-07-06Listing of #ARM Cortex-M0 instructions.
on 02023-07-05explains how to control #OpenOCD by telnetting to port 4444 and typing textual coommands. Discussion of what #asm the #STM32 STM32F103 does and doesn't support. Discussion of linker scripts. Explanation of the #ARM literal pool.
on 02023-07-05lengthy exegesis of #ARM #ABI in #asm as our hero fights with their compiler
on 02023-07-05EABI, the new Linux #ABI for #ARM, is actually the ARM APCS.
on 02023-07-05oh hey #GCC has -fverbose-asm which helps significantly in getting readable #asm for #ARM!
#ARM calling conventions
on 02023-07-05apparently on #ARM when #GCC only has to push LR, it pushes an extra unnecessary temp register onto the stack to ensure SP is 8-byte-aligned at all times, because that’s what the ABI requires, because the ARMv4 strd and ldrd instructions require 8-byte alignment. #asm
oh my, I hadn’t realized that all the Cortex-M #ARM #hardware only supported Thumb-2 #asm. Or that every #STM32 #microcontroller supported SWD for single-stepping with OpenOCD. Apparently to burn the Flash on an STM32 you openocd -f interface/stlink-v2.cfg -f target/stm32f1x.cfg -c "program prog1.elf verify reset exit"? And then to provide a gdbserver on port 3333 you openocd -f interface/stlink-v2.cfg -f target/stm32f1x.cfg?
Slide deck about #ARM #asm. Supposedly the #Raspberry-Pi 2 and 3 (but not 1 and Zero) support #Thumb-2 instructions, and the #STM32 STM32L only supports Thumb-2 (no original ARM fixed-width instruction set). There’s a super sweet #code-density graph on p.35 of the #PDF: 8086 is the champion; PDP-11 and Z80 are almost tied and beat Thumb-2, which beats Thumb, which beats VAX, which beats i386, which beats x86_64, which beats 6502, which beats arm_eabi, which beats the living shit out of ia64.
on 02023-07-04#video from 01987 about the #Acorn #Archimedes and the origin of the #ARM, including an #interview with Sophie Wilson featuring the term “order codes”, and some machine specs for the 305, 310, 410, and 440. It comes with optional built-in “Econet”, which turns out to be 800kbps RS-422. Features footage of PCB rework, pick-and-place machines, and “flow soldering”, which I think is not quite wave soldering. Inspiring examples of what you can do with 4 MIPS, 1 MiB RAM, and I guess a TrueColor display, including real-time 3-D with hundreds of flat-shaded polygons. #manufacturing #history #retrocomputing
on 02023-07-02#PDF #ebook “Archimedes Operating System: A Dabhand Guide” from 01991 #ARM, largely #asm. Covers the whole instruction set in chapter 2, pp. 20–32.
on 02023-07-01LGPL #ARM v2a for a Spartan-6 in #Verilog. #gateware
on 02023-07-01#Tutorial #introduction to #ARM #asm using gas, directed toward #GameBoy Advance hacking. A bit rough-and-ready but only 22000 words. Covers add, ldr, ldmia, b, cmp, mov, lsl, lsr, asr, ror, sub, strh, bl, bx, conditions (-ne, -lt, and -ge), the -s suffix for setting flags, conditional instructions, the (even-bit-shifted) byte-sized immediate limitation, inline shifts, write-back (preincrement and postincrement) addressing mode, and Thumb, and finally the whole instruction set and a GBA optimization guide.
on 02023-07-01#Linux on #AVR #hardware by running #ARM #emulation ("μARM") in the AVR, achieving about 0.01 MIPS
on 02021-01-24notes on the #ARM #Apple M1 CPU
on 02021-01-24commentary on the #ARM proposed sale to #NVIDIA
on 02021-01-24"LiteBSD" is a port of 4.4 #BSD to the PIC32MZ #ARM #microcontroller, which has a paging MMU and half a mebibyte of RAM.
on 02021-01-21playing with #aarch64 #ARM #asm with helloworld in qemu and a cross-compiling toolchain. cc-by-nc-sa
on 02016-10-10Linaro and #ARM working on #Linux scheduler power saving
on 02016-10-07holy shit, SoftBank bought #ARM. I didn’t realize the ARM got funded as a Newton CPU. #business #finance
on 02016-10-07Understanding the NVIC interrupt controller on the #ARM Cortex-M.
on 02016-08-13#Arduino compatible #hardware with Freescale #ARM Cortex-M0s (MK20DX128 and MK20DX256) running at 48MHz or 72MHz, but it costs US$20
on 02016-08-11#aarch64 (64-bit #ARM) desktop #hardware doesn’t exist yet
on 02016-08-02Tessel is a 180MHz #ARM Cortex-M3 LPC1830 board with 32MB of SDRAM and 32MB of Flash that you can program in #JS.
on 02015-11-26Espruino is a STMicroelectronics #ARM Cortex-M3 #microcontroller board that runs #JS for US$25, or US$40 from Adafruit. Reputedly you can run the Espruino firmware on #NodeMCU boards.
on 02015-11-26#ESP8266 #hardware #pdf #datasheet (sort of anyway). 12μA in sleep mode. #ARM Thumb apparently, specifically a Tensilica Xtensa LX3. 80MHz.
on 02015-11-26“#free-software has lost, only amd64, aarch64” (64-bit #ARM), “and armv7 are really supported”, by Miod Vallat.
on 02015-11-25the OWL an open-source fully-programmable FX pedal for #music, which lets you run patches written in C++ or #PureData on your guitar pedal, using an #ARM Cortex-M4. Funded on Kickstarter.
on 02015-11-10