Apparently WDC had a 65C832 32-bit 6502 in the works, but never got it built, so Mike Kohn built one in an #FPGA from the datasheet. #electronics #Verilog
on 02025-08-25#Lisp machine #gateware for the MIT CADR in modern #Verilog. “Boots and runs.” By #lisper (Brad Parker)
on 02024-08-25LGPL #ARM v2a for a Spartan-6 in #Verilog. #gateware
on 02023-07-01now #yosys can synthesize a #KiCad netlist for SSI logic #hardware with #SKiDL, and #GHDL enables it to take #VHDL input instead of just #Verilog.
on 02021-05-29"APIO" is a sort of distribution similar to gEDA: “Open source ecosystem for open #FPGA boards. Apio (pronounced [ˈa.pjo]) is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your #verilog designs.” #hardware #yosys
on 02021-01-13on the #J1 #Forth CPU, optimized for FPGAs (rather than #hardware as such). 200 lines of #Verilog. “Originally designed to run the six WGE100 Ethernet cameras in the Willow Garage PR2 robot.” Amazing: “J1 runs at about 100 Forth MIPS on a typical FPGA. This compares with about 0.1 Forth MIPS for a traditional threaded Forth running on an embedded 8-bit CPU.”
on 02017-03-22J1a SwapForth #video by jamesb beckman101, demonstrating synthesizing the CPU from #Verilog with #IceStorm. Looks like an IceStick. Demonstrates programming it interactively in a tiny #Forth with only 227 words (and a filesystem!) and generating a nice stable 1MHz square wave in software, displayed on his digital oscilloscope. #J1 #hardware
on 02016-06-22