Human Folly about “SKiDL”

index

• SKiDL (github.com):

  "SKiDL" is a Python EDSL for generating a #KiCad netlist for automatic layout. #hardware

  on 02021-05-29
• VHDL to PCB (pepijndevos.nl):

  now #yosys can synthesize a #KiCad netlist for SSI logic #hardware with #SKiDL, and #GHDL enables it to take #VHDL input instead of just #Verilog.

  on 02021-05-29