#Breaking-Taps #video about how he got silicon #electronics fabricated (through #WaferSpace #MPW, not a multi-project chip). He settled on a MOV machine (transport-triggered architecture) called BTTAP, designed it in the Spade #HDL, synthesized it with Yosys and ABC, and simulated it for SKY130. Includes animations of some analog simulations. He tested his RTL (?) in cocotb instead of Verilator and viewed his waveforms with Surfer instead of gtkwave. Then he used LibreLane, which wafer.space provides as a #Nix Flake, to get from a netlist to GDSII. Finally wafer.space got it fabbed through GlobalFoundries’ GF180 process, which I didn’t know had an open-source PDK, in only 3-4 months. Wafer.space got some of the chips packaged as COB with transparent epoxy. He got about 1000 chips. From looking at MPW pricing in the past, I’d estimated that this cost him about US$2500, but I think it was actually US$5000. wafer.space GF180MCU run 3 is in December, early-bird price for a quarter-size chip (1.94 × 2.53 mm) of only US$2000.
on 02026-09-22#Breaking-Taps is fabricating his own 20MHz transport-triggered microprocessor at GlobalFoundries in 180nm using Tim Ansell’s new "wafer.space" #MPW service. Also he’s doing a cubesat and has sold off most of his shop. Also there's a coarser-grained alternative to FPGAs called a "CGRA" which is similar to #Groq’s LPUs.
on 02026-03-12another #hardware #MPW shuttle program similar to CMP, MOSIS, etc. “MUSE SEMICONDUCTOR: It’s not just an MPW. A flexible MPW service to support research. Small minimum areas, frequent tapeouts, PDK and IP access, short cycle times.”
on 02025-06-13another #hardware #MPW shuttle program similar to CMP, MOSIS, etc., by UmbraLogic LLC.
on 02025-06-13#IHP #pricing for their 130nm and 250nm processes. Their #MPW price for the SG13G2 process for which they offer an open-source #PDK is €7300/mm². “minimum area requirement of only 0.8 mm² for all runs with bold shipment times.” However, no shipment times appear to be in bold, and the normal minimum seems to be 10mm². Looks like the tape-in-to-shipment-time delay for MPWs is about 6 months. You get 40 diced samples. I’m guessing you can do about 2.5 transistors per μm² in the 130nm process, so 0.8mm² is about 2 million transistors.
on 02025-02-23This #LibreSOC prototype is 5.5 mm × 5.9 mm and has only 130,000 gates in TSMC’s 180nm process, to be fabbed via Imec’s shuttle service (#MPW, like MOSIS and CMP?), running a subset of the OpenPOWER ISA bolted to the side of a CDC 6600 (!!), using LIP6’s coriolis2 for synthesis and place and route. “The Cell Library used, FlexLib, also sponsored by NLnet, was developed by Staf Verhaegen of Chips4Makers, and is Libre-Licensed. Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout.” This is a pretty appallingly low density, though; that’s about half a million transistors, 16000 per mm², though it’s the same process as Coppermine (02000, 21 million transistors in 80mm², 250k/mm²) or the Alpha 21364 (02003, 152 million transistors in 397 mm², 400k/mm²)
on 02021-11-14"Efabless" is an #MPW shuttle program for open-source #hardware, free because it’s sponsored by Google
on 02021-05-29Europractice’s #MPW pricing starts at €1200 for a 4mm² 0.7μm chip. #hardware
on 02018-10-05