Human Folly about “LibreSOC”

index

• 22Nm powerpi (libre-soc.org):

  #LibreSOC is aiming at a 22nm SoC

  on 02021-11-14
• Libre SoC 180nm power ISA ASIC submitted to Imec for fabrication (openpowerfoundation.org):

  This #LibreSOC prototype is 5.5 mm × 5.9 mm and has only 130,000 gates in TSMC’s 180nm process, to be fabbed via Imec’s shuttle service (#MPW, like MOSIS and CMP?), running a subset of the OpenPOWER ISA bolted to the side of a CDC 6600 (!!), using LIP6’s coriolis2 for synthesis and place and route. “The Cell Library used, FlexLib, also sponsored by NLnet, was developed by Staf Verhaegen of Chips4Makers, and is Libre-Licensed. Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout.” This is a pretty appallingly low density, though; that’s about half a million transistors, 16000 per mm², though it’s the same process as Coppermine (02000, 21 million transistors in 80mm², 250k/mm²) or the Alpha 21364 (02003, 152 million transistors in 397 mm², 400k/mm²)

  on 02021-11-14