#Breaking-Taps #video about how he got silicon #electronics fabricated (through #WaferSpace #MPW, not a multi-project chip). He settled on a MOV machine (transport-triggered architecture) called BTTAP, designed it in the Spade #HDL, synthesized it with Yosys and ABC, and simulated it for SKY130. Includes animations of some analog simulations. He tested his RTL (?) in cocotb instead of Verilator and viewed his waveforms with Surfer instead of gtkwave. Then he used LibreLane, which wafer.space provides as a #Nix Flake, to get from a netlist to GDSII. Finally wafer.space got it fabbed through GlobalFoundries’ GF180 process, which I didn’t know had an open-source PDK, in only 3-4 months. Wafer.space got some of the chips packaged as COB with transparent epoxy. He got about 1000 chips. From looking at MPW pricing in the past, I’d estimated that this cost him about US$2500, but I think it was actually US$5000. wafer.space GF180MCU run 3 is in December, early-bird price for a quarter-size chip (1.94 × 2.53 mm) of only US$2000.
on 02026-09-22“The "Chipalooza" Challenge. Open source analog IP for the SoCs of tomorrow. Five shuttle challenges across three major open-source PDKs. Design an #analog IP block, get it fabricated, and win awards for your effort.
“The goal of Chipalooza Challenge is to provide open source libraries of high-quality analog components useful to designers of SoCs for all three major open source PDKs, enabling cross-platform porting of SoCs and a shared home for the IP that analog designers need. Challenge #1, run by Efabless in 2024, produced dozens of analog circuits for Sky130 across two test chips. The five challenges below continue that work: two more rounds each for Sky130, GF180MCU, and #IHP SG13CMOS5L.”
Similar to #Tiny-Tapeout, I think? Challenge #2, on IHP SG13CMOS5L via IHP, has 28 designs and has schematic review complete. Challenge #3, on GF180MCU via Wafer.Space (#WaferSpace), was only launched on August 17th, but is at “proposal review complete”, so I guess the window to submit a proposal is pretty narrow! Challenge #4, on Sky130 via Chip Foundry, is “expected to launch” in November, and #5, another one on GF180MCU via Wafer.Space, is expected in January, and #6, another one on SG13CMOS5L, is expected in June. #hardware #electronics #PDK
on 02026-09-15#Breaking-Taps is fabricating his own 20MHz transport-triggered microprocessor at GlobalFoundries in 180nm using Tim Ansell’s new "wafer.space" #MPW service. Also he’s doing a cubesat and has sold off most of his shop. Also there's a coarser-grained alternative to FPGAs called a "CGRA" which is similar to #Groq’s LPUs.
on 02026-03-12