“The "Chipalooza" Challenge. Open source analog IP for the SoCs of tomorrow. Five shuttle challenges across three major open-source PDKs. Design an #analog IP block, get it fabricated, and win awards for your effort.
“The goal of Chipalooza Challenge is to provide open source libraries of high-quality analog components useful to designers of SoCs for all three major open source PDKs, enabling cross-platform porting of SoCs and a shared home for the IP that analog designers need. Challenge #1, run by Efabless in 2024, produced dozens of analog circuits for Sky130 across two test chips. The five challenges below continue that work: two more rounds each for Sky130, GF180MCU, and #IHP SG13CMOS5L.”
Similar to #Tiny-Tapeout, I think? Challenge #2, on IHP SG13CMOS5L via IHP, has 28 designs and has schematic review complete. Challenge #3, on GF180MCU via Wafer.Space (#WaferSpace), was only launched on August 17th, but is at “proposal review complete”, so I guess the window to submit a proposal is pretty narrow! Challenge #4, on Sky130 via Chip Foundry, is “expected to launch” in November, and #5, another one on GF180MCU via Wafer.Space, is expected in January, and #6, another one on SG13CMOS5L, is expected in June. #hardware #electronics #PDK
on 02026-09-15The open-source #IHP #PDK middle of last year: “Designs already submitted for production include a delta-sigma modulator put together as part of Boris Murmann’s electronic engineering course at the University of Hawaiʻi at Mānoa, a 24GHz low-noise amplifier (LNA) from Martin Sander at Ulm University, a different LNA targeting cellular devices from a team at the Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), and a simple RISC-V CPU designed by Daniel Schultz and Steffen Reith.” #hardware #electronics
on 02025-02-23#PDF slides on the first year of the #IHP open-source 130nm SG13G2 #PDK. “a 200mm pilot line for state-of-the-art BiCMOS technologies, operated under industry-like conditions, 24/7, for the provision of prototypes and low-volume production runs.” MIM caps are 1.5fF/μm², or 2.1 for copper.
on 02025-02-23#IHP #pricing for their 130nm and 250nm processes. Their #MPW price for the SG13G2 process for which they offer an open-source #PDK is €7300/mm². “minimum area requirement of only 0.8 mm² for all runs with bold shipment times.” However, no shipment times appear to be in bold, and the normal minimum seems to be 10mm². Looks like the tape-in-to-shipment-time delay for MPWs is about 6 months. You get 40 diced samples. I’m guessing you can do about 2.5 transistors per μm² in the 130nm process, so 0.8mm² is about 2 million transistors.
on 02025-02-23#IHP Tiny Tapeout. Mostly just digital #electronics #hardware designs.
on 02025-02-23#IHP 130nm BiCMOS Open Source #PDK for analog, mixed-signal and RF design. Work in progress, but they’re doing their first #Tiny-Tapeout already. “SG13G2 is a high performance BiCMOS technology with a 0.13 μm CMOS process. It contains bipolar devices based on SiGe:C npn-HBT’s with up to 350 GHz transition frequency (fT) and 450 GHz oscillation frequency (fmax).” #electronics #hardware
on 02025-02-23