In addition to the #one-bit computer, Laughton also built #hardware to add 24-bit bank-switching to a #6502, giving it a 16-megabyte memory space, with four 8-bit bank registers in a coprocessor. The K0 bank register is used for all code fetches and, by default, data fetches, but there are “segment prefix” instructions that activate K1 or K2 for a single instruction, and K3 is used for far jumps and far calls. #electronics
on 02023-09-02Jeff Laughton’s original page on the #one-bit #hardware design with the clock line running into the ROM address line. In his case he used 74C374 registers for the state and CD4000 chips for the I/O, and wrapped two of the CD4099 output lines to the CD4051 input multiplexer to give it two bits of RAM. #electronics
on 02023-09-02A #one-bit (?) computer driven by a state machine in EEPROM #hardware; the I/O registers and next-state register are clocked on opposite phases of the clock, and the clock goes to the A0 address line on the EEPROM, so different 8-bit words from the EEPROM drive those two registers. He’s using 74(LS?)574s for the state registers, a 74LS151 for input multiplexing, a 74LS259 for output multiplexing, and a 74(LS?)04 for inverting the clock and reset.
on 02023-09-02